Conformal Coat

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Per IPC and Jstd CC should cover all required areas but it i... - Jun 11, 2019 by QA123

yes, the void should not expose the conductor or bridge the ... - Jun 24, 2019 by sssamw

Thanks ... - Jun 24, 2019 by QA123

QA123

#82770

Conformal Coat | 11 June, 2019

Per IPC and Jstd CC should cover all required areas but it is acceptable to have voids and other anomalies as long as they do not bridge exposed conductors. Am I interpreting it correctly if the drawing states assemble per IPC it has hatched areas. So can I assume that 100%coverage is still achieved if I have a unit with small voids that meet the acceptable criteria for IPC?

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sssamw

#82876

Conformal Coat | 24 June, 2019

yes, the void should not expose the conductor or bridge the conductor, the coating there should be thick as IPC required but you need minimize the voids and bubbles.

ALso for those small chips, a void or bubble on it means possible ECM, normlly should not has void or bubble on it because it's small size.

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QA123

#82877

Conformal Coat | 24 June, 2019

Thanks

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