haloing on SMT PCBs

I work QA at an OEM in Alberta, Canada. I saw earlier posts on the smtnet regarding PCB haloing criteria. I am currently in a dispute with my PCB vendor over the acceptability of haloing (delamination) around plated through holes and vias on a lot of multi layer SMT PCBs they have shipped us. The only document at my disposal is IPC-A-600C (circa 1978). Under that standard they merely identify haloing and state nothing about acceptability levels (does this mean that by that standard no haloing is acceptable?). My vendor claims that haloing has no effect on the fuctionality of the PCB. I tend to disagree as some of the haloed THs are on high stess areas (DIN and Lemo connector pcb mounting/solder joint areas). I have ordered the latest rev. of IPC-600 however, in the mean time, I must respond to this vendor's allogations. Can anyone give me any info as to the current IPC acceptability standards and/or any insight as to potential failure/fatigue that could result from populated, haloed through holes?

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| I work QA at an OEM in Alberta, Canada. I saw earlier posts on the smtnet regarding PCB haloing criteria. I am currently in a dispute with my PCB vendor over the acceptability of haloing (delamination) around plated through holes and vias on a lot of multi layer SMT PCBs they have shipped us. The only document at my disposal is IPC-A-600C (circa 1978). Under that standard they merely identify haloing and state nothing about acceptability levels (does this mean that by that standard no haloing is acceptable?). My vendor claims that haloing has no effect on the fuctionality of the PCB. I tend to disagree as some of the haloed THs are on high stess areas (DIN and Lemo connector pcb mounting/solder joint areas). | I have ordered the latest rev. of IPC-600 however, in the mean time, I must respond to this vendor's allogations. Can anyone give me any info as to the current IPC acceptability standards and/or any insight as to potential failure/fatigue that could result from populated, haloed through holes? Please do get the new guidelines as without them there is little argument against one so informed or ignorant as your best supplier. I would say this: Haloing is delamination as you so correctly stated. Delamination before thermal stress indicates serious process problems effected by a number of possible causes (drilling, poor lamination process management, chemical problems, etc.). What really is at stake here is what happens to bare boards after thermal stress and shock, such as that encountered during assembly operations and during product performance. If the delamination propogates into the hole walls, opens are the effect. This is not permissable, and IPC & MIL-55110 cover these concerns in detail. There is a way to determine whether this condition will cause failure and that is to perform thermal stress and thermal shock testing on the bare boards, or parts of them. Of course, you should always place quality conformance test circuitry on all your panels so they might suffer the consequences, should they arise. This also should be done in accordance with IPC-275 and the appropriate test methods and acceptance guidelines.

Good arguing, Earl Moon

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| I work QA at an OEM in Alberta, Canada. I saw earlier posts on the smtnet regarding PCB haloing criteria. I am currently in a dispute with my PCB vendor over the acceptability of haloing (delamination) around plated through holes and vias on a lot of multi layer SMT PCBs they have shipped us. The only document at my disposal is IPC-A-600C (circa 1978). Under that standard they merely identify haloing and state nothing about acceptability levels (does this mean that by that standard no haloing is acceptable?). My vendor claims that haloing has no effect on the fuctionality of the PCB. I tend to disagree as some of the haloed THs are on high stess areas (DIN and Lemo connector pcb mounting/solder joint areas). | I have ordered the latest rev. of IPC-600 however, in the mean time, I must respond to this vendor's allogations. Can anyone give me any info as to the current IPC acceptability standards and/or any insight as to potential failure/fatigue that could result from populated, haloed through holes? D.Hammond, I am assuming you have received bare PCB's with this defect. This is for unsupported holes. Acceptable -Class 1,2,3 Penetration of haloing or edge delamination does not reduce the distance from the edge of hole to the closest conductor by more than 50% of that specified or more than 2.5mm [0.100 in] if none specified. NonConforming- Class 1,2,3 Penetration of haloing or edge delamination reduces the distance from the edge of the hole to the closest conductor by more than 50% of that specified or more than 2.5mm [0.100 in] if none specified. Only other mention is for board edges and reference to supported holes and vias is not noted (at least to my knowledge). Only other time I've seen what you describe has been caused by washing the assembly before sufficiently cooling it. There is an easy test for this fortunately. If you have hot air handy (heat shrink gun)try heating the assembly and if halos dissapear then you got moisture intrusion as a result of rapid quenching...not good to the parts or assembly. If you are using no clean...??? Maybe you should as Earl or something. Good luck.

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