JTAG CoreCommander - Take command of microcores for PCB test & debug

JTAG CoreCommander - Take command of microcores for PCB test & debug Description:

Device control via internal JTAG access - processor and FPGA cores

While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote 'kernel-centric' testing. Similarly, in the case of today’s Field Programmable Gate Arrays (FPGAs) test engineers can 'bridge' from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a translatorinterface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone Avalon etc.).

CoreCommander routines take control of key processor core (e.g. ARM, PPC, X-scale, Cortex etc.) functions using the built-in emulation/debug functions found in today’s RISC and DSP cores. They have been developed to speed-up board testing and debug by enabling kernel-centric testing. CoreCommander offer two modes of operation:

• Interactive - offering direct control of the core or;
• Python embedded - where controls can be scripted into a complete program.

Please note that CoreCommander modules are priced per core.

JTAG Live Buzz is automatically included for free with this product.

• JTAG control of µprocessors, and DSPs via core debug access
• Most popular cores supported
• Create cluster tests and flash applications

Benefits:

• Overcomes deficiencies in boundary-scan registers
• Works with devices not compliant to IEEE std 1149.x
• Most popular processor cores & FPGAs supported (ARM PPC etc.)
• Code compatible with Python for test scripting
• Low-cost compared to other solutions.

Specifications:

• Supported by JTAG Technologies, JTAG Live and FTDI based controllers/interfaces
• Simple to use interactive GUI to perform core writes/reads
• Processor functions include 'EnterDebug', 'ExitDebug', 'LoadMemory', 'SaveMemory', 'WritePC', 'ReadPC'
• FPGA users benefit from IP access via standard busses Avalon, AMBA, CoreConnect and Wishbone
• Micro Cores supported are: ARM 7/9/11/Cortex M, Freescale PPC, X-scale PXA27x/27x/3xx, TI C2000, Microchip  PIC32 & ST C166
• Works in tandem with JFT-  Python JTAG/boundary-scan routines.