Mar 28, 2011 
Three New Evaluation Kits for the Popular MachXO, ispMACH 4000ZE and Power Manager II Devices Provide Easy Access to I/O Pins
Lattice Breakout Board Evaluation Kits offer a convenient way for users to accelerate hardware evaluation and prototyping by providing easy access by hand to densely spaced PLD I/Os and pre-wired power and programming connections. For common end applications like I/O expansion and bridging, PLDs offer high I/O density at a low cost. This has made PLDs the preferred solution instead of discrete logic ICs or an application processor with more I/Os.
Breakout Boards provide a convenient way to access the fine-pitch pins or balls of a PLD package. For example, the center-to-center spacing of the package balls of the 256-ball BGA package of the MachXO 2280 Breakout Board is only 1.00 mm BSC (Basic Spacing between Centers). Electrical traces of the Breakout Board connect each I/O to header landings that have 2.54 mm (100 mil / 0.1 inch) centered holes. By adding test probes, jumper wires or pin headers to the header landings, engineers can easily evaluate the MachXO sysI/O™ Buffer, ispMACH 4000ZE I/O cells, or POWR1014A voltage monitors, high-voltage FET drivers, and open drain outputs.
Each Breakout Board is 3" x 3" and features a USB B-mini connector for power and programming, an LED array and a prototype area. All Lattice Breakout Boards provide an easy to use platform for evaluating and designing with the MachXO 2280 PLD, ispMACH 4256ZE CPLD or the ispPAC®-POWR1014A Power Manager II. Along with the board and USB programming cable, each kit includes a pre-loaded hardware test program. Using Lattice design tools that are provided free of charge, the user can reprogram the on-board PLD device to evaluate custom designs.
"We’re pleased to offer this new family of Lattice Breakout Boards, as designers have told us this is a key method to make their design process more convenient,” said Gordon Hands, Lattice's Director of Marketing for Low Density and Mixed-Signal Solutions. “These boards significantly reduce the effort and cost required to adopt and evaluate PLD and mixed signal devices. In fact, users can verify correct board operation in minutes and then connect Breakout Boards directly to their prototyping platforms and test equipment. Designers will also appreciate access to the schematic and PCB CAD artwork files available from the Lattice website.
“For this evaluation kit project,” said Hands, “Lattice took advantage of the turnkey services of Lattice LEADER Design Services Partner Axelsys of Fremont, California. Axelsys provided us with a quick time-to-market using their full turnkey product solution with PLD design, PCB schematic and layout design, PCB fabrication and assembly, and kit packaging.”
About the Lattice MachXO, ispMACH 4000ZE and Power Manager II Devices
The MachXO family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for applications traditionally implemented using CPLDs or low-density FPGAs. MachXO PLDs offer the benefits of increased system integration by providing embedded memory, built-in PLLs, high performance LVDS I/O, remote field upgrade (TransFR™ technology) and a low power sleep mode, all in a single-device. For more information about the Lattice MachXO PLD family, visit http://www.latticesemi.com/machxo.
The ispMACH 4000ZE CPLD family is ideal for ultra-low-power, high-volume portable applications. The ispMACH 4000ZE devices offer typical standby current as low as 10µA; ultra-small, space saving 0.4mm pitch Ball Grid Array packages; 3.3V, 2.5V, and 1.8V I/O standards support; and 5V tolerant I/Os. For more information about the Lattice ispMACH 4000ZE CPLD family, visit http://www.latticesemi.com/products/cpldspld/ispmach4000ze.
Power Manager II devices are general-purpose power-supply monitoring and sequence controllers, incorporating both in-system programmable logic and in-system programmable analog functions implemented in non-volatile E2CMOS® technology. Power Manager II devices integrate many power management functions that normally require multiple ICs. For more information about the Lattice Power Manager II family, visit http://www.latticesemi.com/products/powermanager.
Free Lattice design software can be downloaded from the Lattice website at http://www.latticesemi.com/products/designsoftware.
More information regarding Lattice Breakout Board Evaluation Kits is available at
http://www.latticesemi.com/breakoutboards.
Pricing and Availability
The price for all Lattice Breakout Board Evaluation Kits is $29.99. All kits are available for immediate ordering via the Lattice online store at http://www.latticesemi.com/store/eval_boards_mixedsig.cfm (POWR1014A) and http://www.latticesemi.com/store/eval_boards_cpld.cfm (ispMACH4256ZE and MachXO) and through authorized Lattice distributors listed at http://www.latticesemi.com/sales.
Axelsys is a leading Embedded Electronic Design Services (EDS) and Electronic Manufacturing Services (EMS) company with offices in Silicon Valley, CA and Shanghai, China. Markets addressed include Consumer Electronics, Defense, Medical, Networking, Semiconductor, and Test and Measurement.
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions.
