World Class First Time Yield

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With totally stable screen print (solder paste), placement a... - Dec 07, 2003 by

Stability of process is what your measuring so lets not assu... - Dec 08, 2003 by adlsmt

The SMART Group in the UK have a project that's been going f... - Dec 21, 2003 by johnwnz

IMHO, depending on whether its a regular run model, or a pro... - Dec 27, 2003 by

Kevin Gilbraith

#26524

World Class First Time Yield | 7 December, 2003

With totally stable screen print (solder paste), placement and reflow processes, what is a world class target first time yield for good pcbs? How bad is 65% FTY. Your views would be welcome.

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adlsmt

#26536

World Class First Time Yield | 8 December, 2003

Stability of process is what your measuring so lets not assume a stable process(if your process was perfect you would have no defects). With no test a medium complexity board will be around 68.7% (according to Consulogic). I dont have many other sources and they very dramatically depending on how they measure potential defects. Basically it goes up with complexity and opportunities for defect.

i.e. if you have one 144 pin QFP you have 144 potential defects plus pin one orientation and one opportunity for missing part.If you place seventy two 1206 resistors you have the same solder joint count but 72 possibilities for missing part. If you cant place and solder 1206 resistors your in trouble,yet the statistics are with you, if you get an ocasional bridge or bent lead on a QFP your probably average. If your running bottom side surface mount through a wave, unless you have great design guys, expect a few problems.

It would be great if there was a weighted scale on how to grade defect opportunities by actual difficulty but im not aware of any. Most people use PPM so numbers look good, we use FTY to understand what customers would see if we did not test or inspect but that makes it hard to measure the statistical impact of process improvements. We are working to look at both.

IPC has IPC-9261 and IPC-7912 check them out.

I would love to hear others comments. Most likely no one will share numbers out of fear of customer misinterpretation. We do a number of complex boards with over 10% first pass failures and the customers are always freaked out.

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johnwnz

#26694

World Class First Time Yield | 21 December, 2003

The SMART Group in the UK have a project that's been going for almost a year now where they are collating the PPM results for a range of companies and PCB complexities & publishing the averages as a bench mark for memebers. I hear that NEMI are now looking to do a similar thing...

look at http://www.smartgroup.org for details.

JohnW

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Ian Chan

#26727

World Class First Time Yield | 27 December, 2003

IMHO, depending on whether its a regular run model, or a properly designed/setup pilot run model, getting a mean 75%-95% First Pass Yield (FPY%) is possible as a benchmark target. This is derived from your manufacturing history capabilities, and requires the entire Manufacturing team to be collective honest with each other.

Any further improvements gained are due to tweaking away the bugs in either machine/equipmentsetup, design or process-technologies applied.

PMP versus FPY% is subjective, as someone pointed out, dependant on your customer's reactive understanding (or dependancy) to (factual/frictional) statistics.

Personally I favour FPY%, as its liken to buying a box of chocolates. It doesn't matter how many individual pieces inside are rotten, I'd still return the whole box to the shop. So why would we want to do otherwise for electronics PCB assemblies?

My two cents worth.

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