DFPAU - Floating Point Arithmetic Coprocessor

DFPAU - Floating Point Arithmetic Coprocessor Description:

Overview

DFPAU is a Floating Point Arithmetic Coprocessor, designed to assist CPU in performing the floating point arithmetic computations. DFPAU directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn’t require any programming, so it also doesn’t require any modifications made in the main software. Everything is done automatically during software compilation by the DFPAU C driver.
DFPAU was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered together with the DFPAU package.
DFPAU uses the specialized algorithms to compute arithmetic functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, and change sign of a number. The input numbers format is according to IEEE-754 standard single precision real numbers. DFPAU is prepared to use with 8-, 16- and 32-bit processors. Trigonometric functions are supported indirectly, because they are computed as set of add, multiply and divide operations by software subroutines.
DFPAU is a technology independent design that can be implemented in a variety of process technologies.

Features

■ Direct replacement for C float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
■ C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
■ No programming required
■ IEEE-754 Single precision real format support – float type
■ Flexible arguments and result registers location
■ Performs the following functions:
■ FADD, FSUB – addition, subtraction
■ FMUL, FDIV – multiplication, division
■ FSQRT – square root
■ FCHS, FABS – change of sign, absolute value
■ FXAM – examine input data
■ FUCOM – comparison
■ Exceptions built-in routines
■ Masks each exception indicator:
■ Precision lack PE
■ Underflow result UE
■ Overflow result OE
■ Invalid operand IE
■ Division by zero ZE
■ Denormal operand DE
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Tech Specs

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Compliant Standard - IEEE-754

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix, Cyclone II, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-4 SX, Virtex-4 LX, Virtex-4 FX, Spartan-3E, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,