DFPMU - Floating Point Coprocessor

DFPMU - Floating Point Coprocessor Description:

Overview

DFPMU is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn’t require any programming, so it also doesn’t require any modifications made in the main software. Everything is done automatically during software compi-lation by the DFPMU C driver.
DFPMU was designed to operate with DCD’s DP8051, but can also operate with any other 8-, 16- and 32-bit processor. Drivers for all popular 8051 C compilers are delivered to-gether with the DFPMU package.
DFPMU uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign of a number and trigonometric functions: sine, cosine, tangent and arctangent. It has built-in conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. DFPMU supports single precision real numbers, 16-bit and 32-bit integers. DFPMU is prepared to use with 8-, 16- and 32-bit processors.
DFPMU is a technology independent design that can be implemented in a variety of process technologies.

Features

■ Direct replacement for C float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
■ C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
■ No programming required
■ IEEE-754 Single precision real format support – float type
■ 16-bit word and 32-bit short integers format supported – integer types
■ Flexible arguments and result registers location
■ Performs the following functions:
■ FADD, FSUB – addition, subtraction
■ FMUL, FDIV – multiplication, division
■ FSQRT – square root
■ FCHS, FABS – change of sign, absolute value
■ FXAM – examine input data
■ FUCOM – comparison
■ FSIN, FCOS – sine, cosine
■ FTAN – tangent
■ FATAN – arctangent
■ FILDW, FILD – 16-bit, 32-bit integer to float
■ FISTW, FIST – float to 16-bit, 32-bit integer
■ Exceptions built-in routines
■ Masks each exception indicator:
■ Precision lack PE
■ Underflow result UE
■ Overflow result OE
■ Invalid operand IE
■ Division by zero ZE
■ Denormal operand DE
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Tech Spec

FPGA - Altera, Xilinx, Lattice

Type - Soft Firm  

Compliant Standard - IEEE-754

Availability - now

FPGA Technology:

Altera: Stratix II, Stratix, Cyclone II, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-4 SX, Virtex-4 LX, Virtex-4 FX, Spartan-3E, Spartan-3,
Actel: SX-A, ProASICPLUS, Axcelerator,