DI2CMS - I2C Bus Interface - Master/Slave

DI2CMS - I2C Bus Interface - Master/Slave Description:

Overview

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CMS core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master or slave transmitter/receiver depending on working mode determined by microprocessor/microcontroller. The DI2CMS core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. The DI2CMS supports all the transmission speed modes. Built-in timer allows operation from a wide range of the clk frequencies.
The DI2CMS is a technology independent VHDL or VERILOG design that can be implemented in a variety of process technologies and can be fully customized accordingly to customer needs.
DI2CMS is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

Features

■ Conforms to v.2.1 of the I2C specification
■ Master mode
■ Master operation: Master transmitter, Master receiver
■ Support for all transmission speeds: Standard (up to 100 kb/s), Fast (up to 400 kb/s), High Speed (up to 3,4 Mb/s)
■ Arbitration and clock synchronization
■ Support for multi-master systems
■ Support for both 7-bit and 10-bit address-ing formats on the I2C bus
■ Build-in 8-bit timer for data transfers speed adjusting
■ Slave mode
■ Slave operation: Slave transmitter, Slave receiver
■ Supports 3 transmission speed modes: Standard (up to 100 kb/s), Fast (up to 400 kb/s), High Speed (up to 3,4 Mb/s)
■ Allows operation from a wide range of input clock frequencies
■ User-defined data setup time
■ User-defined timing (data setup, start setup, start hold, etc.)
■ Simple interface allows easy connection to microprocessor/microcontroller devices
■ Interrupt generation
■ Fully synthesizable
■ Static synchronous design
■ Positive edge clocking and no internal tri-states
■ Scan test ready

Tech Specs

Type - Soft Firm  

Availability - now

TSMC - Silicon Proven : 130nm (CL013G)

UMC - Silicon Proven : 130nm

FPGA Technology:

Altera: Stratix II, Stratix GX, Stratix, HardCopy, FLEX 10K, Cyclone, APEX II, APEX 20KE, APEX 20KC,
Xilinx: Virtex-II Pro, Virtex-4 SX, Virtex-4 LX, Virtex-4 FX, Spartan-3E, Spartan-3,
Actel: SX-A, RTSX-SU, RTAX-S/SL/DSP, ProASICPLUS, MX, eX, Axcelerator,