Jun 23, 2010 
Cost of Test is one of the biggest challenges for the semiconductor test industry today. The development of next generation equipment is driven by the need for increased efficiency. Enhanced tester capabilities allow shorter test times and higher parallelism. Handlers try to keep pace with higher parallelism but mismatch with speed.
Currently, for many applications the tester, the most expensive part of the test cell, is idle, waiting for the handler. The urgent challenge is to optimize tester utilization in order to benefit from higher parallelism and shorter test times.
This presentation will focus on the effects of optimizing those parameters one by one. Additionally it will elaborate on the interdependencies of the parameters and analyze application specific requirements. Finally, it the presentation will postulate new concepts that today’s and future tester generations require to fully leverage their advanced capabilities.
Günther Jeserer studied Electrical Engineering and Information Technology at the Technical University of Munich. In 1984 he joined Multitest Electronic Systems in Rosenheim, Germany. After holding several positions such as software engineer, project and product manager, he is now the Business Unit Manager for Gravity and P&P Handlers at Multitest.
Multitest Elektronische Systeme GmbH, Rosenheim is one of the world’s leading manufacturers of test equipment for semiconductor. Under the brands Multitest, ECT Interface Products and Harbor Electronics Multitest market test handlers, contactors and ATE printed circuits boards. It has offices and branches in North America, Singapore, Malaysia, the Philippines, Taiwan, China and Thailand. Multitest has an annual turnover of greater than 100 million EURO and currently employs more than 750 people.
www.multitest.com
